Dielectric absorption (DA) is a form of capacitor non-ideality wherein the capacitor has additional memory of its history (beyond its expected capacitance), and tends in the direction of trying to return to a previous value of voltage across it. This memory (also called soakage) is attributed to a charge which becomes trapped in the dielectric of the capacitor over time, and takes time to escape as well. As such, it varies substantially with the physical construction of the capacitor, both among discrete types, and various implementations available in integrated circuits. These charge-trapping mechanisms also often have large temperature dependencies, varying by an order of magnitude or more over typical integrated circuit operating temperature ranges.
In the context of a system integrating a capacitive sample-and-hold (S/H), the DA of the hold capacitor causes the value of a given sample to trend towards the value of previous samples as it is held. A simplified example of such an S/H circuit is shown as circuit 100 in FIG. 1. S/H circuit 100 takes an input voltage at input terminal 120 and produces a sample-and-held output at output terminal 121. Input buffer 110 buffers the input voltage. Hold capacitor 101 is periodically connected to the buffered input by sampling switch 105. Output buffer 115 isolates the hold capacitor 101 from loads applied to the output terminal 121.
The circuit operates in two alternating phases. The first is a track phase during which switch 105 is closed. In the track phase, the input buffer 110 forces the voltage across the hold capacitor 101 to be equal to the input voltage. Output buffer 115 then causes the output voltage 121 to be equal to the hold capacitor voltage and thus the input voltage.
The circuit transitions from a track phase to a hold phase when switch 105 is opened at a sampling moment. In the hold phase, the hold capacitor maintains the approximate voltage present at the sampling moment, and this voltage is presented at the output. If the hold capacitor 101 has DA, the charge trapping mechanism represents storage of charge which retains information about voltages applied to the hold capacitor at times before the sampling moment. As the hold phase progresses, that charge storage will affect the value of voltage on the hold capacitor, which will manifest as a deviation of the output voltage from the intended behavior.
Where the S/H function is part of a sampling analog-to-digital converter (ADC), DA will cause the ADC's output for a given sample to be affected by the values of previous samples. FIG. 2 shows an exemplary ADC circuit 200 that includes voltage input 220 and digital code output 221. An array of switches 207 operates to couple an array of capacitors 201 to the input 220, reference voltage terminal 222, or ground under the control of respective control signals 223 produced by control logic 217. The capacitor array 201 is also coupled to the input of comparator 215, and may be connected to ground by sampling switch 205.
The ADC circuit 200 operates as a successive-approximation (SAR) ADC in two primary phases. The first acquisition phase is analogous to the tracking phase of the circuit 100. In this phase, sampling switch 205 is closed, and switch array 207 is configured to couple the capacitor array 201 to input voltage 220. Thus, the capacitors of array 201 have the input voltage imposed across them.
The circuit transitions from the acquisition phase to the conversion phase (analogous to the hold phase of circuit 100) by opening sampling switch 205 at a sampling moment. Switch array 207 is then operated to connect capacitors 201 to the reference voltage terminal 222 or ground on the basis of the outputs of comparator 215, as determined by control logic 217 in a successive approximation process, ultimately determining the digital output 221.
During this conversion phase, the voltage presented to the comparator is determined by the voltage across the capacitors at the sampling moment and the voltage applied by switches 207. If capacitors 201 have DA, the charge trapping mechanism represents storage of charge which retains information about voltages applied to the capacitors at times before the sampling moment. As the conversion phase progresses, that charge storage will affect the value of voltage on presented to the comparator, which will cause a deviation of the output digital code from the ideal value.
In some applications, this effect may not be deleterious, particularly as DA is typically a fairly linear phenomenon. However, in any situation where the S/H is being multiplexed between channels, the DA causes a low-frequency crosstalk between the channels which may be limiting.
A first known technique for reducing DA is typically present in any S/H design. The effect of DA from one sample upon the following sample is directly dependent upon the ratio of time in which the capacitor holds the input signal to the time in which it tracks the input signal. Thus, one may decrease the sample-to-sample memory by decreasing that ratio (i.e. increasing the track time relative to the hold time). Unfortunately, changing this ratio substantially requires large changes to the timing characteristics, for example slowing down an ADC's sample rate by a factor comparable to the factor of improvement in crosstalk, and in many cases such a timing compromise is unacceptable.
A second known technique for reducing DA provides an analog cancellation term. For example, an explicit network of resistors and capacitors may be exposed to the same voltage stimuli as the hold capacitor. The resistors are chosen to model the long-term storage effects present in the hold capacitor due to DA, and then used to inject a small correction term into the primary signal path.
A conceptually similar third technique may be used when the S/H circuit is part of an ADC. In particular, a digital record of previous conversion outputs can be kept, and used to adjust the digital output of the present conversion in a predetermined fashion.
The second and third techniques suffer from the problem of attempting to cancel the DA effect with an unrelated external term. Given that the DA effect may vary dramatically with temperature, it is at best difficult to construct a term which provides good cancellation across a wide range of temperatures.
Therefore, it would be desirable to develop a DA-suppressing technique that would avoid disadvantages of known techniques.